As integrated circuit (IC) devices (also referred to as semiconductor devices) advance technologically, these devices generally evolve to become physically smaller. In order to meet design constraints associated with these smaller devices, advanced patterning techniques have been developed. For example, multiple patterning techniques, such as double patterning and/or triple patterning may be used to meet design constraints in smaller devices (e.g., at the 14 nanometer (nm) node, and potentially beyond this node).
However, in the case of multiple patterning, decomposing a layout into, e.g., two exposures may not guarantee the desired patterning in the completed IC. That is, it is also critical to ensure that the density of shapes on both masks (in the double-patterning example) remains balanced, in order to ensure uniform etch behavior. However, it can be difficult to enforce these shape density parameters during the design process because IC designers are not responsible for particularly large areas of the IC. Conventional approaches of designing layouts for multiple patterning processes are deficient in producing the desired result.